As the feature size of CMOS devices is continuously reducing, the application of a gate dielectric with a high dielectric constant (K) and a metal gate electrode has become an inevitable trend. The high-K dielectric has a thicker physical thickness for a given Equivalent Oxide Thickness (EOT), by which it is possible to greatly reduce the gate tunneling leakage current. However, the conventional polysilicon gate is incompatible with the high-K gate dielectric due to the sever Fermi Pinning Effect, so it must be replaced with the novel metal gate electrode. With the metal gate, it is possible not only to avoid the depletion effect of the polysilicon gate and to reduce the gate resistance, but also to avoid the boron penetration, so as to improve the device reliability. However, there are still some problems to be addressed in integrating the metal gate on the high-K gate dielectric, such as problems of thermal stability and interface state. In particular, the Fermi Pinning Effect imposes a great challenge on obtaining of a properly low threshold voltage required by the nano-scale CMOS devices, especially PMOS devices.
In order to obtain a proper threshold, work functions of an N-type transistor and a P-type transistor should be in the proximity of the bottom of a conduction band of Si (about 4.1 eV) and in the proximity of top of a valence band of Si (about 5.2 eV), respectively. A TiN metal gate has become a promising candidate for the metal gate due to its low resistivity and excellent thermal and chemical stability. In the integration technology, in order to reduce the difficulty of etching and to increase as less as possible the complexity of the existing CMOS process, an inserted metal gate stack structure (i.e. a polysilicon/metal gate stack structure) is usually used instead of a pure metal gate to implement the integration of the high-K and metal gate materials. However, since the high-temperature process in directly depositing a polysilicon layer on the TiN metal gate will cause reaction between the TiN metal gate and the polysilicon layer, this has become an obstacle of the metal gate/high-K integration technology.